1. Field of the Invention
The present invention relates to a semiconductor memory device which operates synchronously with a basic clock signal, and, in particular, to a clock-synchronous semiconductor memory device wherein data can be input and output at high speed, and to a method for accessing this device.
2. Description of the Prior Art
The inventors of the present invention have previously proposed (Japanese Patent Application No. 3-255354) a semiconductor memory device, wherein, an address is input at a specific cycle of the basic clock signal synchronized with a basic clock signal supplied to the system, and then input and output of data commences after a specific number of cycles, counted from this specific cycle.
In the operation of this semiconductor memory device, a cycle in which no data is output extends from the provision of a row address until the output of the data. Accordingly, during the output of data synchronized with the clock signal, for example, when the row address is changed, a cycle is produced in which no data is output. This cycle is explained below in detail. Also, in the case of a column address as well, it is not appropriate that the column address be changed frequently and random access characteristics be provided.
This point will now be explained in detail. In the make-up of a memory cell array of a semiconductor memory, there is a matrix structure of rows and columns in which a plurality of memory cells are systematically arranged.
Generally, a series of cells related to a word line is selected from a row address, and the data from one cell in the selected word line is selected from a column address.
For this reason, the time required from deciding the row address until the output of the data must be longer than the time required from deciding the column address until the output of the data. Therefore, when a new row address is set during the output of a series of data items synchronized with the clock signal, time is required for accessing the row with the new row address. As a result, the clock-synchronous data output is interrupted. This is referred to as a cycle in which no data is output.
In particular, with a DRAM, precharge time is always necessary prior to the access of a new row address, therefore, the output of individual items of data is interrupted for a long time.
FIG. 1 is a chart specifically showing this cycle in which no data is output. In the chart, first, the memory access is commenced at a specific column in a memory cell group by the provision of a row address (CLK1) when a row enable control signal/RE is at a low level in the cycle, and the provision of a column address (CLK3), for example, at the second cycle following this cycle, when a column enable control signal/CE is at a low level in the cycle. This data passes through several cycles until output by data transfer to an external circuit becomes possible, for example, at the fourth cycle after the column address has been provided (CLK7). In FIG. 1, the Dout signals are output.
Following this, data is output at each cycle according to a predetermined order. Cell data designating a string of data after the row address has been provided, is related to the row address provided at the beginning. This takes some time in a DRAM because the cell data is sensed by access from a row address and is held in a sense amplifier, but because only the data held in the sense amplifier is read out by access to the column address, the read-out can be accomplished in a comparatively short time. In the case where the control signal/RE is at the "L" level and a new row address is set, the data held in the sense amplifier up to this time is reset, and a sense-related precharge is required to sense the new row data.
After this precharge has been carried out, a sensing operation is performed and new column data is held in the sense amplifier. During the term of the precharge for the row which is newly designated, data related to the previous row address is collected in the output register, and the read-out portion can be continuously output.
However, after the output of this part is completed, the output operation is halted because the data to be output is no longer prepared. As shown on the chart, data output can be continued up to the third cycle (CLK15) following the cycle in which the new row address is set (CLK12). In this example, in data output of the new row address, a space for two cycles (CLK16 and CLK17) of data output is produced because a minimum of six cycles has elapsed.
As can be understood from the foregoing explanation, when the designation of the row address is changed in a conventional clock-synchronous semiconductor memory device, the output of data synchronized with the clock signal is interrupted, resulting in the problem that the clock-synchronous memory function cannot be fully demonstrated.
In addition, data is output for a change in the column address, as shown in FIG. 2, and, in the clock-synchronous semiconductor memory device disclosed by the inventor of the present invention (see FIG. 3) one string of data is transmitted as a package from a memory cell group 32 to a serial register 37 so that it is not possible to arbitrarily modify the column address within the required cycle in outputting data of the length of the serial register 37. Specifically, in this case, access of the serial register 37 is normally carried out in a fixed order for high speed access of the memory cell, and it becomes possible to determine the first part of the access of the register 37 only during a bulk transmission of data to the register 37.
Accordingly, the feature of random accessibility of as many bits as possible of the serial register 37 disappears at that column.